The present invention related to a single supply voltage nonvolatile memory device with row decoding.
As is known, memory devices are typically organized as an array, in which word lines connect gate terminals of the memory cells located on the same row, and bit lines connect drain terminals of the memory cells located on the same column.
The rows of the memory array are addressed by means of a row decoder, which receives at an input a coded address and has the purpose of biasing the word line of the row each time addressed at a stable and precise voltage, the value of which depends upon the type of operation carried out on the memory cells of that particular row (reading, programming, verifying, erasing).
In some memory devices, the memory array has an organization of the type comprising global word lines and local word lines. In particular, the memory array comprises global word lines and a plurality of local word lines for each global word line, the local word lines being connected to the corresponding global word line through respective switching stages which, when they are turned on, have the purpose of enabling transfer of the voltage present on the global word line to the respective local word line and to which the memory cells are then physically connected.
A global row decoder addresses the global word lines and a local row decoder addresses the local word lines. In particular, the global row decoder is directly connected to the global word lines and each time biases the line or lines selected, whilst the local row decoder controls the switching stages so as to enable selective connection between the local word lines and their respective global word line.
A switching stage of the type referred to above is, for example, described in the European Patent Application No. 98830570.2, filed on Sep. 30, 1998 in the name of the present applicant, and its circuit diagram is shown in FIG. 1.
In particular, the switching stage, designated as a whole by 1, is connected between a global word line 4, driven by a respective output global driving stage 5 forming part of the global row decoder (not illustrated), and a local word line 6, presents a CMOS type structure, and comprises a PMOS transistor 7 and an NMOS transistor 9 having source terminal and, respectively, drain terminal connected together to the global word line 4, drain terminal and, respectively, source terminal connected together to the local word line 6, and gate terminals receiving respective mutually complementary control signals PCH and NCH, one of which is supplied by a respective local output driving stage (not shown) forming part of the local row decoder (not shown either), whilst the other is obtained from the former via an inverter.
The NMOS transistor 9 further has a bulk terminal biased at a voltage VNEG, which is equal to a ground voltage during the reading and programming phases of the memory cells and is equal to a negative erasing voltage, for example xe2x88x928 V during the erasure phase, whilst the PMOS transistor 7 has a bulk terminal biased at a voltage VPCX, which typically assumes a value of approximately 6 V during the reading phase and a value of approximately 1.5 V during the erasing phase, and presents a staircase waveform with a preset step during the programming phase, in which the initial value and the final value of the staircase depend upon the type of memory cells used; for example, for four level memory cells (i.e., memory cells capable of storing 2 bits per cell), the programming voltage varies between 1.5 and 9 V with a step of approximately 300 mV.
Moreover connected to the local word line 6 is a drain terminal of a discharging NMOS transistor 11 having source terminal connected to ground, bulk terminal biased at the voltage VNEG, and gate terminal receiving a control signal DSC, and having the purpose, when it is on, of keeping the local word line 6 at the ground voltage.
In addition, during the reading and programming phases, the global word lines 4 and the local word lines 6 selected must also be biased at the voltage VPCX, which is therefore supplied at an input, as supply voltage, both to the global row decoder and to the local row decoder in order to bias the respective internal circuitries.
It is also known, however, that memory devices are typically of the single supply voltage type; i.e., they receive from outside a single supply voltage VCC having a value of, for example, between 2.5 and 3.8 V.
Consequently, the voltage VPCX referred to above, assuming values even greater than the supply voltage VCC, is generated inside the memory device by means of a voltage elevator circuit, generally referred to as xe2x80x9cvoltage boosterxe2x80x9d or xe2x80x9ccharge pumpxe2x80x9d, supplied by the supply voltage coming from outside and supplying at an output a boosted voltage higher than the supply voltage, which, since it is not very stable in voltage, is supplied at an input of a voltage regulator, which in turn supplies at an output the voltage VPCX referred to above, which is stable in voltage and presents the above mentioned values.
From an electrical point of view, connected to the output of the voltage regulator is a very high parasitic capacitive load, which cannot be reduced substantially in that it is due to components that are physically required for carrying out both global and local row decoding and for biasing the bulk terminals of the PMOS transistors of the switching stages. Note, for example, that in a flash multilevel 64 bit memory, the parasitic capacitance connected to the output of the voltage regulator is of the order of 500 pF.
The presence of a high capacitive load connected to the output of the voltage regulator brings about a noticeable slowing down in the operation of the voltage regulator.
In fact, when a row of the memory array is not addressed, the corresponding word line is connected to ground, so that the capacitance associated to it is discharged; when, however, this row is addressed, the corresponding global word line is in fact connected to the output of the voltage regulator, the output voltage of which undergoes a sudden decrease caused by the well known phenomenon of charge sharing, which takes place between the overall capacitance connected to the output of the voltage regulator and the capacitance of the word line.
This situation is further aggravated by the dynamic consumption of the local output driving stages of the local row decoder, which, since they must necessarily be of reduced dimensions to be physically positioned between two adjacent local word lines, have a simple structure and require a switching current (crowbar current) that is rather high, unlike the output global driving stages of the global row decoder, which, since they are not subject to such stringent dimensional constraints, have a more complex structure and larger dimensions, and hence have a smaller dynamic consumption.
Consequently, the presence of such a high capacitive load connected to the output of the voltage regulator causes a considerable slowness in the recovery of the output voltage supplied by the voltage regulator, i.e., a considerable slowness in the restoration of the voltage supplied by it within an interval that may enable optimal reading of the memory cells; this slowness may lead, in certain cases, to a degradation of the time of access to the memory and, above all, the carrying out of wrong readings.
The presence of such a high capacitive load connected to the output of the voltage regulator has unfavourable consequences also in the programming phase of the memory cells, during which, as is known, in order to guarantee adequate accuracy in the programmed levels, a staircase voltage is applied to the word line. In particular, the high capacitive load causes the overall time for charging the word line, i.e., the time necessary for biasing the word line to each one of the levels of the staircase voltage, proves rather long.
According to principles of the present invention, a memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.